drm/i915/pps: Store the power cycle delay without the +1

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The code initializing the power sequencing delays is a bit
hard to follow. One confusing thing is that we keep doing the
+/-1 adjustment for the hardware register value in several places.
Simplify this a bit by doing the adjustment only when reading or
writing the actual register.

This also matches how the LVDS code does things.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241106215859.25446-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

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Ville Syrjälä 2024-11-06 23:58:52 +02:00

parent da5bb8974c

commit 57ecdc5521

1 changed files with 12 additions and 16 deletions

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drivers/gpu/drm/i915/display/intel_pps.c

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