clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL

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The CLK_SET_RATE_PARENT flag is added to clocks between the EPLL
and the audio subsystem clock controller so that the EPLL's output
frequency can be set indirectly with clk_set_rate() on a leaf clock.
That should be safe as EPLL is normally only used to generate clock
for the audio subsystem.
With this change we can avoid passing the EPLL clock to the ASoC
machine driver.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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Sylwester Nawrocki 2017-07-21 16:21:02 +02:00

parent 7df45a532c

commit 599cebea93

1 changed files with 8 additions and 7 deletions

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drivers/clk/samsung/clk-exynos5420.c

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