soc: xilinx: vcu: register PLL as fixed rate clock

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Currently, xvcu_pll_set_rate configures the PLL to a clock rate that is
pre-calculated when probing the driver. To still make the clock
framework aware of the PLL and to allow to configure other clocks based
on the PLL rate, register the PLL as a fixed rate clock.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-8-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Michael Tretter 2021-01-21 08:16:51 +01:00 • committed by Stephen Boyd

parent f1bc982e7c

commit 5a2b2e1341

2 changed files with 19 additions and 2 deletions

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2

drivers/soc/xilinx/Kconfig

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19

drivers/soc/xilinx/xlnx_vcu.c

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