drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2

Browse source

For DP pll settings, there is only two golden configs.  Instead of
running through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.

v2: Rework on the intel_limit compiler warning. (Jani)

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[danvet: Fix up checkpatch issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Chon Ming Lee 2013-09-04 01:30:38 +08:00 • committed by Daniel Vetter

parent 9dd4ffdf39

commit 65ce4bf5a1

2 changed files with 12 additions and 18 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

20

drivers/gpu/drm/i915/intel_display.c

View file

10

drivers/gpu/drm/i915/intel_dp.c

View file