RISC-V: Clear HSTATUS.HU on CPU initialization

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The RISC-V privileged specification does not mandate HSTATUS reset
values, leaving the HU bit potentially set after hardware reset.
When HU=1, hypervisor instructions (HLV/HLVX/HSV) can execute in
U-mode to access guest memory, which may cause unintended behavior
if not explicitly controlled.

Clear HSTATUS.HU during CPU initialization to ensure hypervisor
instructions are only available in HS-mode, preventing unexpected
guest memory access from U-mode code.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://patch.msgid.link/20260924-hstatus_hu-v2-1-7e970f5f1d8d@sifive.com
Cc: stable@vger.kernel.org
[pjw@kernel.org: capitalized RISCV_ISA_EXT_h to fix build; added stable cc]
Signed-off-by: Paul Walmsley <pjw@kernel.org>

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Yong-Xuan Wang 2026-10-05 19:02:38 -06:00 • committed by Paul Walmsley

parent 148ab873d8

commit 6694612317

5 changed files with 20 additions and 0 deletions

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2

arch/riscv/include/asm/cpufeature.h

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12

arch/riscv/kernel/cpufeature.c

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2

arch/riscv/kernel/setup.c

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2

arch/riscv/kernel/smpboot.c

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arch/riscv/kernel/suspend.c

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