perf/x86/intel: Update event constraints and cache_extra_regsfor CWF

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Update perf hard-coded event constraints and cache_extra_regs[] for
Clearwater Forest according to the latest CWF perfmon events (V1.02).

An important difference is that CWF introduce new extra register values
for the L3 cache OCR events, so define darkmont specific
dkt_hw_cache_extra_regs[] array.

CWF perfmon events:
https://github.com/intel/perfmon/blob/main/CWF/events/clearwaterforest_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-12-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-05-15 14:11:43 +08:00 • committed by Peter Zijlstra

parent 7ae5f58517

commit 66cc29745f

1 changed files with 29 additions and 1 deletions

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arch/x86/events/intel/core.c

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