clk: meson: add axg misc bit to the mpll driver

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On axg, the rate of the mpll is stuck as if sdm value was 4 and could not
change (expect for mpll2 strangely). Looking at the vendor kernel, it
turns out a new magic bit from the undocumented HHI_PLL_TOP_MISC register
is required.

Setting this bit solves the problem and the mpll rates are back to normal

Fixes: 78b4af312f ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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This commit is contained in:

Jerome Brunet 2018-01-19 16:42:36 +01:00

parent 2fa9b361e5

commit 6c00e7b760

3 changed files with 28 additions and 0 deletions

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20

drivers/clk/meson/axg.c

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7

drivers/clk/meson/clk-mpll.c

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1

drivers/clk/meson/clkc.h

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