arm64: fix midr range for Cortex-A57 erratum 832075

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Register MIDR_EL1 is masked to get variant and revision fields, then
compared against midr_range_min and midr_range_max when checking
whether CPU is affected by any particular erratum. However, variant
and revision fields in MIDR_EL1 are separated by 16 bits, so the min
and max of midr range should be constructed accordingly, otherwise
the patch will not be applied when variant field is non-0.

Cc: stable@vger.kernel.org # 3.19+
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Bo Yan <byan@nvidia.com>
[will: use MIDR_VARIANT_SHIFT to construct upper bound]
Signed-off-by: Will Deacon <will.deacon@arm.com>

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Bo Yan 2015-03-31 21:30:48 +01:00 • committed by Will Deacon

parent 905e8c5dca

commit 6d1966dfd6

1 changed files with 2 additions and 1 deletions

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arch/arm64/kernel/cpu_errata.c

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