PCI: tegra: Support per-lane PHYs

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The current XUSB pad controller bindings are insufficient to describe
PHY devices attached to USB controllers. New bindings have been created
to overcome these restrictions. As a side-effect each root port now is
assigned a set of PHY devices, one for each lane associated with the
root port. This has the benefit of allowing fine-grained control of the
power management for each lane.

Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2015-11-11 18:25:59 +01:00

parent 13541cc3d4

commit 6fe7c187e0

1 changed files with 227 additions and 17 deletions

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drivers/pci/host/pci-tegra.c

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