arm64: perf: Enable PMCR long cycle counter bit

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With the long cycle counter bit (LC) disabled the cycle counter is not
working on ThunderX SOC (ThunderX only implements Aarch64).
Also, according to documentation LC == 0 is deprecated.

To keep the code simple the patch does not introduce 64 bit wide counter
functions. Instead writing the cycle counter always sets the upper
32 bits so overflow interrupts are generated as before.

Original patch from Andrew Pinksi <Andrew.Pinksi@caviumnetworks.com>

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

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Jan Glauber 2016-02-18 17:50:13 +01:00 • committed by Will Deacon

parent d0aa2bffcf

commit 7175f0591e

1 changed files with 16 additions and 5 deletions

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arch/arm64/kernel/perf_event.c

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