clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks

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Add the CLK_PLLDSI0_CSDIV and CLK_PLLDSI1_CSDIV fixed-factor clocks to
the r9a09g047 SoC clock driver.

These clocks are required to enable DSI and RGB output support.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/4d5b4ddad89770447b3818381d5353f5065b72b5.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Tommaso Merciai 2026-04-08 12:36:50 +02:00 • committed by Geert Uytterhoeven

parent 0e1597c688

commit 7a9e1c485c

2 changed files with 19 additions and 0 deletions

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18

drivers/clk/renesas/r9a09g047-cpg.c

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1

drivers/clk/renesas/rzv2h-cpg.h

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