clk: renesas: r9a07g044: Add mux and divider for G clock

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G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.

This patch adds a mux and divider for getting different rates from
this clock sources.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2021-12-03 11:51:50 +00:00 • committed by Geert Uytterhoeven

parent 98ee8b2f66

commit 7ef9c45a23

2 changed files with 10 additions and 0 deletions

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6

drivers/clk/renesas/r9a07g044-cpg.c

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4

drivers/clk/renesas/rzg2l-cpg.h

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