drm/i915: Clarify VLV PLL p1 limits

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For some reason there's a sort of off by one issue with the p1 divider.
The actual p1 limits according to
VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm is 2-3, so we should
just say that instead of saying 1-3 and avoiding the 1 via the choice of
comparison operator.

I don't know why we're using different p1 limits for intel_limits_vlv_dac
and intel_limits_vlv_hdmi, but let's preserve that for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2013-09-24 21:26:25 +03:00 • committed by Daniel Vetter

parent 27e639bf02

commit 811bbf0544

1 changed files with 3 additions and 3 deletions

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drivers/gpu/drm/i915/intel_display.c

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