clk: renesas: r9a09g056-cpg: Add clock and reset entries for OSTM instances

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Introduce a new fixed divider .pllcln_div16 which is sourced from PLLCLN
and add PCLK module clocks gtm_0_pclk through gtm_7_pclk for OSTM0-7.
Add corresponding reset lines GTM_0_PRESETZ through GTM_7_PRESETZ to
control the OSTM instances.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-05-13 16:46:32 +01:00 • committed by Geert Uytterhoeven

parent bfb0bc6bdf

commit 82a0bc727c

1 changed files with 26 additions and 0 deletions

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drivers/clk/renesas/r9a09g056-cpg.c

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