KVM: MIPS/T&E: Report correct dcache line size

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Octeon CPUs don't report the correct dcache line size in CP0_Config1.DL,
so encode the correct value for the guest CP0_Config1.DL based on
cpu_dcache_line_size().

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

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This commit is contained in:

James Hogan 2017-03-14 10:25:47 +00:00

parent 1c506c9c10

commit 867f4da752

1 changed files with 8 additions and 0 deletions

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8

arch/mips/kvm/trap_emul.c

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