drm/i915: No LLC_MLC for HSW.

Browse source

The mid-level cache or as it's more commonly referred to now as L3, is
not setup this way on HSW.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Ben Widawsky 2012-09-21 16:54:14 -07:00 • committed by Daniel Vetter

parent 17f10fdc01

commit 8693607ae4

1 changed files with 7 additions and 3 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

10

drivers/gpu/drm/i915/i915_gem_gtt.c

View file