clk: thead: th1520-ap: Poll for PLL lock and wait for stability

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All PLLs found on TH1520 SoC take 21250ns at maximum to lock, and their
lock status is indicated by register PLL_STS (offset 0x80 inside AP
clock controller). We should poll the register to ensure the PLL
actually locks after enabling it.

Furthermore, a 30us delay is added after enabling the PLL, after which
the PLL could be considered stable as stated by vendor clock code.

Fixes: 56a48c1833 ("clk: thead: add support for enabling/disabling PLLs")
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>

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Yao Zi 2025-11-20 13:14:11 +00:00 • committed by Drew Fustini

parent 5f352125f8

commit 892abfbed7

1 changed files with 32 additions and 2 deletions

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drivers/clk/thead/clk-th1520-ap.c

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