drm/i915/cx0: Read out the Cx0 PHY SSC enabled state

Browse source

Read out the C10, C20 PHY PLLs SSC enabled state, so the PLL HW/SW state
verification can check this state as well.

C10 PHY PLLs program some PLL registers zeroed out for the non-SSC case,
while programming non-zero values to the same registers for the SSC
case, so check that these PLL registers being zero or non-zero matches
the PLL's overall SSC-enabled state (stored in the
intel_c10pll_state::ssc_enabled flag).

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-11-mika.kahola@intel.com

...

This commit is contained in:

Imre Deak 2025-11-17 12:45:40 +02:00 • committed by Mika Kahola

parent 5df82b1792

commit 8ad92b0733

1 changed files with 25 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

25

drivers/gpu/drm/i915/display/intel_cx0_phy.c

View file