drm/amd/display: Program DSC during timing programming

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[why]
Link or DIG BE can't be exposed to a higher stream bandwidth than they
can handle. When DSC is required to fit the stream into the link
bandwidth, DSC has to be programmed during timing programming to ensure
this. Without it, intermittent issues such as black screen after S3 or a
hot-plug can be seen.

[how]
Move DSC programming from enabling stream on link to timing setup.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Nikola Cornij 2020-02-26 14:53:54 -05:00 • committed by Alex Deucher

parent 4c631826e0

commit 8cc426d79b

4 changed files with 17 additions and 4 deletions

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11

drivers/gpu/drm/amd/display/dc/core/dc_link.c

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2

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

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7

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

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1

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

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