x86/speculation: Add virtualized speculative store bypass disable support

Browse source

commit 11fb068349 upstream

Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD).  To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f.  With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.

Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

This commit is contained in:

Tom Lendacky 2018-05-17 17:09:18 +02:00 • committed by Greg Kroah-Hartman

parent 72f46c229a

commit 8e1c285a05

4 changed files with 18 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

1

arch/x86/include/asm/cpufeatures.h

View file

2

arch/x86/include/asm/msr-index.h

View file

4

arch/x86/kernel/cpu/bugs.c

View file

13

arch/x86/kernel/process.c

View file