dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator

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Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Xingyu Wu 2023-07-13 19:38:56 +08:00 • committed by Conor Dooley

parent 14b14a57e6

commit 9b3938c0b8

3 changed files with 121 additions and 0 deletions

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87

Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml

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18

include/dt-bindings/clock/starfive,jh7110-crg.h

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16

include/dt-bindings/reset/starfive,jh7110-crg.h

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