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Allwinner clock changes for 4.21
Our usual clock driver changes for 4.21. The major patches in that pull request are: - Sigma Delta modulation for the A33 audio clocks - Support for the F1c100s SoC - Rework of the oscillator tree - H6 display engine clocks -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXAqKgwAKCRDj7w1vZxhR xeh2AP4m3zMvyKItQ+5coJ1eznvEKTFpfVAVZItN4cqY111ZhgD+NQsxBQ6DTkRD 0805wCBO0X3kjj5817QAR7bpEU+BPgo= =McQv -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clock changes from Maxime Ripard: - Sigma Delta modulation for the A33 audio clocks - Support for the F1c100s SoC - Rework of the oscillator tree - H6 display engine clocks * tag 'sunxi-clk-for-4.21' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL clk: sunxi-ng: h3: Allow parent change for ve clock clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: h6: Set video PLLs limits clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock
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