Fix for PLL rate calculation on rk3328 and SET_RATE_PARENT flag

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for the display clock on rk3066.
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Merge tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

Fix for PLL rate calculation on rk3328 and SET_RATE_PARENT flag
for the display clock on rk3066.

* tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
  clk: rockchip: fix frac settings of GPLL clock for rk3328

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This commit is contained in:

Stephen Boyd 2019-02-05 14:07:52 -08:00

parent bfeffd1552 491b00ff69

commit a49ba41c53

2 changed files with 8 additions and 8 deletions

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4

drivers/clk/rockchip/clk-rk3188.c

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12

drivers/clk/rockchip/clk-rk3328.c

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