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a49ba41c53
for the display clock on rk3066. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxS/XkQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgRhTB/9cYpXRFDSm4yBytb/iD10gHTjG6CUfcOl5 4sHpIw09UPzb2JVeoDREXfgjQUOoQG2jgnj9mFsYcVP86keTq6h9yrBVIn2lUI3/ TBqp75UBBkwkQVgA+30RE1SaU/djqLzpgicoktPViTonZ7RJgiVGe7rsO3CH5chb n6i4MQruv4L6dahz6aHM4eDLZVYTrSMJCbxhQ45augpmVbERHRWGTkAly6VPPkMC lL024ixMm3gt8qwBbpBHYv9+egkba/26PiFLEFdfIaMb1TVyPUl983PDft7NAqIm 8iKX7cCoWoc5xTacBLA//IN59rzheIHxjOO1mtjq8b5C+uGzyfXj =yXoJ -----END PGP SIGNATURE----- Merge tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Fix for PLL rate calculation on rk3328 and SET_RATE_PARENT flag for the display clock on rk3066. * tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks clk: rockchip: fix frac settings of GPLL clock for rk3328 |
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Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.