clk: tegra: Fix WARN_ON in PLL_RE registration

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This fixes two things.

- Read the correct IDDQ register
- Check the correct IDDQ bit position

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Bill Huang 2015-06-18 17:28:38 -04:00 • committed by Thierry Reding

parent afff455cf4

commit a4ca2b2fe7

1 changed files with 2 additions and 1 deletions

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3

drivers/clk/tegra/clk-pll.c

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