clk: tegra: Add sor_safe clock

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The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2015-04-20 15:13:36 +02:00

parent eede7113aa

commit a91bb605ec

2 changed files with 5 additions and 0 deletions

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1

drivers/clk/tegra/clk-id.h

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4

drivers/clk/tegra/clk-tegra210.c

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