clk: stm32mp1: add Post-dividers for PLL

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Each PLL has 3 outputs with post-dividers.

pll1_p is dedicated for Cortex-A7
pll1_q is not connected
pll1_r is not connected

pll2_p is dedicated for AXI
pll2_q is dedicated for GPU
pll2_r is dedicated for DDR

pll3_p is dedicated for mcu
pll3_q is for Peripheral Kernel Clock
pll3_r is for Peripheral Kernel Clock

pll4_p is for Peripheral Kernel Clock
pll4_q is for Peripheral Kernel Clock
pll4_r is for Peripheral Kernel Clock

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>

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Gabriel Fernandez 2018-03-08 17:53:59 +01:00 • committed by Michael Turquette

parent c6cf4d3248

commit a97703c59f

1 changed files with 221 additions and 0 deletions

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drivers/clk/clk-stm32mp1.c

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