drm/i915/display: Add DG2 MPLLB DPLL manager support

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Add DG2-specific DPLL manager infrastructure for MPLLB-backed port PLLs.

Introduce PLL id mapping, DG2-specific DPLL callbacks for
enable/disable/readout/frequency calculation, and manager callbacks
for compute/get/dump/compare. The platform is not switched over yet.

DG2's PLL-to-encoder lookup prefers the active encoder using the PLL,
but fall back to a matching encoder for the fixed port-to-PLL mapping
when no active user can be identified.

This keeps the active-user fix for operational paths while allowing
readout and verification paths to resolve the PHY even when
pll->active_mask does not identify an active user.

v2: Use intel_encoder_is_dig_port() to filter out
    MST virtual encoders (Imre)

Assisted-by: Copilot:claude-sonnet-4-6
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> (v1)
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Link: https://patch.msgid.link/20260630115336.1059976-3-mika.kahola@intel.com

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This commit is contained in:

Mika Kahola 2026-06-30 11:53:34 +00:00

parent 75eef2123c

commit a97ec4236f

2 changed files with 232 additions and 0 deletions

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210

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

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22

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

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