clk: mediatek: mt8192: use MUX_CLR_SET

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The mfg_pll_sel mux has neither a clock gate nor an update register,
and upd_ofs is stored as u32, so the -1 truncates to 0xFFFFFFFF.

While upd_shift being -1 (as s8) prevents the update path from
executing at runtime, the bogus upd_ofs value is still stored in the
struct.

Use MUX_CLR_SET to avoid passing sentinel values to wrongly-typed
fields.

Fixes: 710573dee3 ("clk: mediatek: Add MT8192 basic clocks support")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Daniel Golle 2026-03-26 05:10:47 +00:00 • committed by Stephen Boyd

parent 820ea6936b

commit aec2d3caae

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drivers/clk/mediatek/clk-mt8192.c

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