clk: renesas: r9a07g044: Add GbEthernet clock/reset

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Add ETH{0,1} clock/reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2021-09-22 16:51:45 +01:00 • committed by Geert Uytterhoeven

parent 32897e6fff

commit c11d7f5126

1 changed files with 10 additions and 0 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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