MIPS: lantiq: timer irq can be different to 7

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The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq
code to be able to handle this.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4229/

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John Crispin 2012-08-16 08:09:20 +00:00

parent 61fa969f27

commit c2c9c788b9

1 changed files with 16 additions and 3 deletions

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arch/mips/lantiq/irq.c

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