dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions

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Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx
and RZ/G2L HW(Rev.0.50) manual.

Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and
separate reset from module clocks in order to handle them efficiently.

Update the SCIF0 clock and reset index in the SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com
[geert: Squashed 3 commits]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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This commit is contained in:

Biju Das 2021-06-26 09:13:39 +01:00 • committed by Geert Uytterhoeven

parent 668756f729

commit c3e67ad6f5

5 changed files with 278 additions and 119 deletions

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4

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

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drivers/clk/renesas/r9a07g044-cpg.c

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drivers/clk/renesas/renesas-rzg2l-cpg.c

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drivers/clk/renesas/renesas-rzg2l-cpg.h

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include/dt-bindings/clock/r9a07g044-cpg.h

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