clk: imx8mq: remove SYS PLL 1/2 clock gates

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Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.

Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de
Fixes: b04383b6a5 ("clk: imx8mq: Define gates for pll1/2 fixed dividers")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

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Lucas Stach 2021-05-28 20:01:35 +02:00 • committed by Abel Vesa

parent 18a50f82cd

commit c586f53ae1

2 changed files with 18 additions and 57 deletions

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19

include/dt-bindings/clock/imx8mq-clock.h

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