drm/i915/gt: Set BLIT_CCTL reg to un-cached

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Blitter commands which do not have MOCS fields rely on
cacheability of BlitterCacheControlRegister which was mapped
to index 0 by default.Once we changed the MOCS value of
index 0 to L3 WB, tests like gem_linear_blits started failing
due to a change in cacheability from UC to WB.

Program and place the BlitterCacheControlRegister in
build_aux_regs().

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210903092153.535736-4-ayaz.siddiqui@intel.com

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Ayaz A Siddiqui 2021-09-03 14:51:51 +05:30 • committed by Ramalingam C

parent d79a1d7131

commit c6b248489d

2 changed files with 50 additions and 2 deletions

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43

drivers/gpu/drm/i915/gt/intel_workarounds.c

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9

drivers/gpu/drm/i915/i915_reg.h

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