can: mcp251xfd: introduce struct mcp251xfd_tx_ring::nr and ::fifo_nr and make use of it

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This patch removes the hard coded assumption that the TX ring uses
hardware FIFO 1. This allows the hardware FIFO 1 to be used for RX and
the next free FIFO for TX.

This gives the opportunity to minimize the number of SPI transfers in
the IRQ handler. The read of the IRQ status register and RX FIFO
status registers can be combined into single SPI transfer. If the RX
ring uses FIFO 1, the overall length of the transfer is smaller than
in the original layout, where the RX FIFO comes after the TX FIFO.

Link: https://lore.kernel.org/all/20220217103826.2299157-2-mkl@pengutronix.de
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

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This commit is contained in:

Marc Kleine-Budde 2021-05-21 19:51:32 +02:00

parent 2a68dd8663

commit c912f19ee3

5 changed files with 26 additions and 12 deletions

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4

drivers/net/can/spi/mcp251xfd/mcp251xfd-chip-fifo.c

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4

drivers/net/can/spi/mcp251xfd/mcp251xfd-dump.c

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22

drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c

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4

drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c

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4

drivers/net/can/spi/mcp251xfd/mcp251xfd.h

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