clk: renesas: r8a779a0: Add Z0 and Z1 clock support

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Add support for the Z0 and Z1 (Cortex-A76 Sub-system 0 and 1) clocks,
based on the existing support for Z clocks on R-Car Gen3.

As the offsets of the CPG_FRQCRB and CPG_FRQCRC registers on R-Car V3U
differ from the offsets on other R-Car Gen3 SoCs, we cannot use the
existing R-Car Gen3 support as-is.  For now, just make a copy, and
change the register offsets.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/2112e3bc870580c623bdecfeff8c74739699c610.1625219713.git.geert+renesas@glider.be

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Geert Uytterhoeven 2021-07-02 11:58:05 +02:00

parent c11d7f5126

commit cc3e8f97bb

1 changed files with 158 additions and 0 deletions

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drivers/clk/renesas/r8a779a0-cpg-mssr.c

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