clk: renesas: r8a779g0: Add SCIF clocks

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Add the module clocks used by the Serial Communication Interfaces with
FIFO (SCIF) on the Renesas R-Car V4H (R8A779G0) SoC.

Based on a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/a6ab466cfdac377106494c00b811a60151cb1825.1665147497.git.geert+renesas@glider.be

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Geert Uytterhoeven 2022-10-07 15:10:02 +02:00

parent f5684bde03

commit ceb22d9312

1 changed files with 4 additions and 0 deletions

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drivers/clk/renesas/r8a779g0-cpg-mssr.c

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