drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid

Enable this only for Sienna Cichild
since only Navi12 and Sienna Cichlid support SRIOV

Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rohit Khaire 2021-06-04 11:32:42 -04:00 • committed by Alex Deucher
commit cec7e80fbf