clk: samsung: exynos7: Fix CMU TOP1 block

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As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1.
This patch corrects it.
This also adds xxx_FSYS11 to be saved/restore during s2r cycles.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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Alim Akhtar 2015-08-26 09:00:42 +05:30 • committed by Sylwester Nawrocki

parent fa9f3a5264

commit cfc7588a31

1 changed files with 15 additions and 9 deletions

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drivers/clk/samsung/clk-exynos7.c

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