OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change

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Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency.  Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

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Paul Walmsley 2009-06-19 19:08:27 -06:00 • committed by paul

parent c9812d042a

commit d0ba3922ae

4 changed files with 14 additions and 8 deletions

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4

arch/arm/mach-omap2/clock34xx.c

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8

arch/arm/mach-omap2/sram34xx.S

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4

arch/arm/plat-omap/include/mach/sram.h

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6

arch/arm/plat-omap/sram.c

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