clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2

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Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
to R9A07G044_CLK_P0_DIV2.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719143811.2135-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2021-07-19 15:38:10 +01:00 • committed by Geert Uytterhoeven

parent 9800190881

commit d28b1e03dc

1 changed files with 2 additions and 1 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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