clk: meson: split divider and gate part of mpll

The mpll clock is a kind of fractional divider which can gate. When the RW operation have been added, enable/disable ops have been mistakenly inserted in this driver. These ops are essentially a poor copy/paste of the generic gate ops. This change removes the gate ops from the mpll driver and inserts a generic gate clock on each mpll divider, simplifying the mpll driver and reducing code duplication. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2026-09-26 18:16:26 +00:00 · 2018-02-12 15:58:43 +01:00 · 2018-02-12 15:58:43 +01:00 · d610b54f77
commit d610b54f77
parent 722825dcd5
8 changed files with 197 additions and 118 deletions
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h