drm/i915/dp: Account VSC SDP in min guardband

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The transmission line for VSC SDP is the same as AS SDP
(EMP_AS_SDP_TL) when AS SDP is enabled. Otherwise, it uses the
second line of delayed vblank. For VSC without AS SDP, this
requires 2 lines plus 1 setup line, so the VRR guardband must be
at least 3 lines.

When both AS SDP and VSC SDP are enabled, the guardband
requirement is already accounted for during optimized guardband
calculation and the final guardband validation in
compute_config_late(). However, when VSC SDP is enabled without
AS SDP, the VSC SDP requirement is not checked explicitly.

Even in the unlikely case where the optimized guardband is
clamped to vblank length, it cannot fall below 5 lines since such
modes are already pruned. Still, for completeness, account for
VSC SDP and ensure a minimum guardband of 3 lines.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260915164657.3429075-13-ankit.k.nautiyal@intel.com

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Ankit Nautiyal 2026-09-15 22:16:53 +05:30

parent bfa5972380

commit d6795b64b1

1 changed files with 7 additions and 0 deletions

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drivers/gpu/drm/i915/display/intel_dp.c

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