clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros

Browse source

Rename the macros CLK_PLL2_DIV16->CLK_PLL2_DIV2_8 and
CLK_PLL2_DIV20->CLK_PLL2_DIV2_10 to match the clock tree mentioned in
the hardware manual(Rev.1.00 Sep, 2021).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211110082019.28554-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

...

This commit is contained in:

Biju Das 2021-11-10 08:20:18 +00:00 • committed by Geert Uytterhoeven

parent 073da9e7c7

commit dc446cba43

1 changed files with 6 additions and 6 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

12

drivers/clk/renesas/r9a07g044-cpg.c

View file