drm/amd/display: update dpp/disp clock from smu clock table

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[ Upstream commit 2e72fdba8a ]

[Why]
The reason some high-resolution monitors fail to display properly
is that this platform does not support sufficiently high DPP and
DISP clock frequencies

[How]
Update DISP and DPP clocks from the smu clock table then DML can
filter these mode if not support.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

Paul Hsieh 2025-07-23 11:51:42 +08:00 • committed by Greg Kroah-Hartman

parent 09250b6e73

commit e3d2a19a2c

2 changed files with 33 additions and 3 deletions

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16

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

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20

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

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