arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588

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VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.

For now only HDMI0 output is supported, hence add the related PLL clock.

Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Cristian Ciocaltea 2025-02-04 14:40:08 +02:00 • committed by Heiko Stuebner

parent d0f1773877

commit eb4262203d

1 changed files with 4 additions and 2 deletions

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arch/arm64/boot/dts/rockchip/rk3588-base.dtsi

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