coresight tmc etr: Setup AXI cache encoding for read transfers

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If the ETR supports split cache encoding (i.e, separate bits for
read and write transfers) unlike the older version (where read
and write transfers use the same encoding in AXICTL[2-5]).
This feature is not advertised and has to be described by the
static mask associated with the device id.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Suzuki K Poulose 2017-08-02 10:22:15 -06:00 • committed by Greg Kroah-Hartman

parent cd407abd5e

commit ebab6a7db2

2 changed files with 15 additions and 1 deletions

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6

drivers/hwtracing/coresight/coresight-tmc-etr.c

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10

drivers/hwtracing/coresight/coresight-tmc.h

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