clk: renesas: r9a09g011: Add WDT clock and reset entries

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Add WDT0 clock and reset entries to CPG driver.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Phil Edworthy 2022-05-18 16:01:05 +01:00 • committed by Geert Uytterhoeven

parent e55c4481e7

commit efded37b42

1 changed files with 3 additions and 0 deletions

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drivers/clk/renesas/r9a09g011-cpg.c

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