clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller

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Add clock and reset entries for SPI Multi I/O Bus Controller.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210928130132.15022-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2021-09-28 14:01:32 +01:00 • committed by Geert Uytterhoeven

parent cc3e8f97bb

commit f294a0ea9d

2 changed files with 21 additions and 0 deletions

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18

drivers/clk/renesas/r9a07g044-cpg.c

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3

drivers/clk/renesas/rzg2l-cpg.h

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