x86/intel_rdt: Support L3 cache performance event of Broadwell

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Broadwell microarchitecture supports pseudo-locking. Add support for
the L3 cache related performance events of these systems so that
the success of pseudo-locking can be measured more accurately on these
platforms.

Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: fenghua.yu@intel.com
Cc: tony.luck@intel.com
Cc: vikas.shivappa@linux.intel.com
Cc: gavin.hindman@intel.com
Cc: jithu.joseph@intel.com
Cc: dave.hansen@intel.com
Cc: hpa@zytor.com
Link: https://lkml.kernel.org/r/36c1414e9bd17c3faf440f32b644b9c879bcbae2.1529706536.git.reinette.chatre@intel.com

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Reinette Chatre 2018-06-22 15:42:29 -07:00 • committed by Thomas Gleixner

parent 8a2fc0e1bc

commit f3be1e7b2c

2 changed files with 66 additions and 0 deletions

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56

arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c

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10

arch/x86/kernel/cpu/intel_rdt_pseudo_lock_event.h

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